Introduction
With the rapid development of communications technology, increasingly complex and transient signals of developers an indispensable tool for measurement - digital oscilloscope performance higher and higher requirements. Maximize real-time sampling rate and waveform capture capability to become a digital oscilloscope manufacturers foreign and domestic focus of the study, real-time sampling rate and waveform capture rate of increase has inevitably brought a large number of high-speed waveform data transmission, storage and disposal problems. Therefore, as a digital oscilloscope data processing and system control center, the microprocessor performance is critical. This selection of TI's dual-core DSP OMAP-L138 as the design of microprocessors, and implementation of a digital oscilloscope microprocessor hardware design.
The basic framework of digital oscilloscope
Use more current digital oscilloscope DSP, FPGA or microprocessor-based embedded microprocessor + FPGA architecture. Although flexible embedded microprocessor-based FPGA, we can fully develop and validate the design, easy to upgrade and FPGA simple peripheral circuits. But the type of FPGA is the high-end FPGA, high prices and supply channels is rare, and is not suitable for low-cost digital oscilloscopes. If used alone DSP, although its powerful data processing capability, high speed, but the ability to control the DSP is not obvious, and the digital oscilloscope's sampling rate higher and higher, DSP internal data flow deceleration and can not do caching, when the design adopted High real-time sampling rate ADC, have to use storage resources more frequently and more abundant within the DSP, but these are generally expensive DSP, and are not suitable for low cost digital oscilloscopes. Therefore, the microprocessor + FPGA architecture is the design of the preferred solution.
After the signal conditioning analog channels after the op amp to ADC device; ADC converter input signals into digital signals and after the corresponding FPGA cache and pretreatment; microprocessor sampled associated digital signal processing and computing ; Finally, the waveform displayed on the screen to complete an acquisition process. Acquisition process while continuously monitoring the input signal triggers the circuit to see if the trigger condition occurs, the trigger conditions determine the starting position of the waveform, the trigger system to ensure the stability of the measured waveform can be displayed on the screen.
Microprocessor selection
The design of real-time sampling rate of up to 2Gsps, need real-time processing of waveform data processor is very high. At the same time the microprocessor control to achieve the analog channels, high speed ADC sampling control, the waveform data storage control, LCD display control. Therefore, both powerful data processing ability and excellent control of the microprocessor into the design of choice.
Based on these requirements, the design chosen TI's OMAP-L138 DSP. This chip is the TI in 2009 launched a high-performance processor chips. The chip features are as follows:
1, using the C6748 DSP core and dual-core ARM9 core structure, the units up to 300 MHz core frequency. Using on-chip ARM9, developers can take advantage of DSP cores support real-time processing of high strength calculation, while allowing for non-real-time tasks ARM.
2, abundant internal memory resources. ARM core which has 16KB of internal procedures for Cache and 16KB L1 data Cache; DSP core with the secondary cache structure, including procedures for 32KB of L1 Cache, 32KB Data Cache and 256KB L2 unified mapping of SRAM, the secondary cache structure can be for all loading, storage and processing requests for services for the CPU can provide efficient, high-speed data sharing; In addition, in between the ARM core and DSP core also up to 128KB of on-chip RAM, can be ARM core, DSP core and the chip memory access.
3, rich peripheral resources. EMIFA include a port, can be accessed by 16bit SDRAM or NOR / NAND Flash; 1 个 EMIFB mouth, can be accessed by 16bit of DDR2 (the highest frequency of 150MHz) or 16bit mDDR (the highest frequency of 133MHz); 3 个 UART interface; two SPI interfaces ; two I2C interfaces; an EMAC controller; a USB2.0 interface and a USB1.1 interface; an LCD controller; a SATA controller; a uPP interface; a VPIF interface; 4 64-bit general purpose timers. Rich peripheral resources not only provide for the oscilloscope PC, portable USB interface device communication interface, but also greatly reduce the size of DSP peripheral circuit design,
4, low power consumption. With 1.2V core voltage, 1.8V or 3.3VI / O interface, voltage, power consumption in deep sleep mode, only 6mW, normal operation mode, power consumption is about 420mW.
In addition OMAP-L138 is floating, fixed-compatible DSP, using hardware to perform floating-point operations can be completed in a single cycle, the advantages of high accuracy especially when complex algorithms for real-time processing of complex algorithms to provide a guarantee. OMAP-L138 and C6748 DSP can be pin-for-pin compatible, enabling customers to adopt a variety of different processors at the same time the development of products with different characteristics.
System hardware design digital oscilloscope
The design chosen Atmel's ADC AT84AD001, the chip has two channels, each channel sampling rates up to 1Gsps, put together to achieve real-time sampling rate 2Gsps; FPGA company Xilinx Spartan-3A selection series XC3S400A chip, the chip has 8064 logic cells, 360Kbit block RAM, 56Kbit distributed RAM, 4 digital clock management (DCM), 311 个 I / O port. 300KB capacity SRAM chips on a plug-in FPGA used for deep storage, as SRAM memory capacity much larger than the FPGA internal FIFO buffer can store more data waveform, which waveform can be observed for more details. Capacity using 64Mbit SPI Flash storage oscilloscope Brown need to save the data, such as program code, Boot loader program, in English fonts, startup screen and so on.
In this design, the measured signal into the analog channels after conditioning into the ADC, ADC on the analog signal sampling, quantization, go to the deceleration FPGA data flow and data synchronization, and then asked to select into the FPGA memory depth, or stored in the internal FIFO off-chip SRAM, FIFO, or until the internal FPGA chip SRAM effective after the full mark, DSP reads the sampled data into the DDR2 SDRAM, and complete a series of complex processing and computing, such as FFT, interpolation and filtering, and then stored in the DDR2 expand the storage area within the display, to be displayed again when required by the DSP read the data in memory within the integrated LCD controller through the use of DMA transfer of data to the LCD display, to complete a collection procedure.
OMAP-L138 DDR2/Mobile DDR controller integrated in the operating frequency of 150MHz can add the operating frequency of 133MHz DDR2 SDRAM, or the Mobile DDR. This design uses DDR2 SDRAM as a system-level waveform data after the buffer. Than SDRAM, DDR2 SDRAM read and write speed is not only a substantial increase in storage capacity is greatly expanded, the oscilloscope waveform data so it can store more and more of the waveform observed in detail, to improve the complex signal oscilloscopes and transient signals capture probability. The design selected Micron's DDR2 SDRAM DDR2 800 memory chips, model MT47H64M16, capacity of 1Gbit, core operating voltage of 1.8V, the core operating frequency is 400MHz, the OMAP-L138 DDR2 controller within the maximum operating frequency of 150MHz, Therefore, this system requires down-to use DDR2.
DDR2 signal lines include clock, data and command of three parts. The DDR2 controller design by the differential clock CLK + and CLK-to DDR2,, difference between the clock and then match a 100Ω resistor to eliminate the clock and limit the drive current of the burr; data to complete some of the major data, including data lines DQ [15:0], data synchronization signal DQS (data lines corresponding to the design LDQS low eight, UDQS the corresponding data line high eight), the data signal shield DM (in the burst write transfers the data stored in shielded, LDM corresponds to the low eight data bits DQ [7:0], UDM corresponds to data line high eight DQ [15:8]), the design of the DQS signal and the signal on the DM series with a 22Ω resistor and filter interference from role in enhancing the signal quality; command section includes the row address strobe RASn, column address strobe CASn, write enable signal WEn, chip select signal CSn, CKE clock enable signal and chip enable internal termination resistors ODT, mainly to complete addressing, the composition of various control commands and memory initialization. The design of the DDR2 controller without termination, so will the ODT DDR2 SDRAM DDR2 chip signal directly to ground so that the terminating resistor is not valid.
Ethernet interface circuit design
Signals with the oscilloscope measurements, the information and measurement results easy saving and sharing becomes increasingly important. If the digital oscilloscope to provide Ethernet interface, developers can easily measure the sharing of data and results through the network, remote debugging; waveform data can be uploaded to the network PC, PC, achieved in the waveform data processing, analysis and display.
OMAP-L138 within the integrated Ethernet controller (EMAC) support the IEEE802.3 standard, supports 10Base-T and 100Base-T Ethernet standard two, there are two full-duplex and half duplex modes to choose from, MII and RMII provides two Ethernet interfaces.
Use LAN8710 Ethernet transceiver, the Ethernet transceiver provides two Ethernet MII and RMII interfaces. This design uses EMAC MII interface LAN8710 and interconnection. MII interface includes a data interface between a MAC and PHY management interface. Data interfaces, including the respective transmitter and receiver for two independent channels. Each channel has four data lines, clock and control signals, including the management interface is a two-signal interface: a clock signal, and the other is the data signal. Through the management interface to monitor and control the upper PHY. MDC clock management interface provided by the EMAC, up to 8.3MHz; data signal MDIO is a bi-directional interface with the MDC synchronization, control transceiver and collect status information from the transceiver. The information can be collected, including link status, transmission speed and choice, power, low-power sleep mode, TX / RX mode selection, auto-negotiation control, loop-back mode control.
Conclusion
This design has the following advantages: data processing and system control synchronously; microprocessor internal storage resource-rich, and the use of secondary cache structure, the system response speed; peripheral rich in resources, such as the USB interface, provides, RS232 and Ethernet interfaces network interface with the PC, Internet interface, to facilitate the oscilloscope collected waveform data in the PC, real-time processing and online debugging; external memory is rich in resources, with 1Gbit capacity DDR2 SDRAM for the latter level waveform data cache and display data buffer , can store more waveform data, waveform observed for more details. Thus, the use of the oscilloscope system can significantly increase data processing capacity of digital oscilloscopes and waveform capture rate, the whole response time will also be a higher level.
Made in China, the U.S. CPSC on the implementation of digital clamp multimeter or recall
December 14, 2010, the U.S. Consumer Product Safety Commission and the Extech Instruments Corporation today announced a domestic digital clamp multimeter or a voluntary recall.
The recalled products Extech digital clamp model EX612, EX613, EX622 and EX623; universal form of the product model for the EX540, EX542 and EX570. "Extech" and the front of the product model number, serial number marked on the back of the serial number with the letter "A" at the beginning of the products are no longer included in the recall. Universal Form Clamp, or the number from January 2008 ~ November 2010 hardware stores nationwide sold, priced at 150 to 300 U.S. dollars / month.
The number of the recalled product is about 5100. Reasons for the recall, if the current speed is too low, the number or multimeter clamp voltage can not be measured accurately the number of users are caused by electric shock. Up to now, Extech Instruments has received 1 from the clamp or voltage meter displays the number of error reports, there is no personal injury accidents.
To this end, the U.S. Consumer Product Safety Commission advises consumers to immediately stop using the recalled digital clamp or multimeter, and contact with the Extech Instruments free replacement clamp or multimeter.
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